A technique called hierarchical design may be used to design a large scale integrated circuit, such as a CPU, a SoC, and the like. According to the hierarchical design technique, the entire circuit that is a design target may be segmented into a plurality of regions called blocks, and one or a plurality of designers may design each of the blocks. At a stage when the design operation with respect to all of the blocks is completed, the blocks may be merged and the circuit may be assembled as a chip. Then, various analysis including inspections, tests, evaluations, and the like may be performed with respect to the entire chip. The design operations with respect to all of the blocks may be performed in parallel according to the hierarchical design technique, however, a highly accurate check, test, evaluation, and the like may be difficult to perform until the circuits are assembled into the chip. The design may be performed by securing a region in which route (or wiring) is prohibited, that is, a route prohibited region, at a boundary between mutually adjacent blocks, in order to avoid a spacing error and the like between the mutually adjacent blocks.
When an inclusion relationship exists among the plurality of blocks designed by the hierarchical design technique, there is a proposed method that makes reference to timing distributing design information (for example, Japanese Laid-Open Patent Publication No. 2002-149730). However, according to this proposed method, it may be difficult, during the design operation of the blocks, to reflect information of blocks in other hierarchical levels that are not in the inclusion relationship to the design of the blocks.
Hence, the following problems may occur in the conventional circuit designing method using the hierarchical design technique.
First, according to the conventional circuit designing method using the hierarchical design technique, the CAD may automatically secure the route prohibited region between the blocks in order to avoid redesigning caused by the spacing error, crosstalk noise error, and the like when merging the blocks. For this reason, the number of routes that may be used may decrease. In addition, because the route prohibited region is provided with a margin that may avoid the error even when the adjacent block or the route is arranged at a closest location, the utilization efficiency of available space may be poor.
Second, according to the conventional circuit designing method using the hierarchical design technique, a highly accurate analysis may be difficult to perform unless after the blocks are merged. Consequently, the redesigning may be required, and reflecting the redesigning to the analysis may be required. As a result, it may take a relatively long time for the design to converge. For example, the design operation may include creating an internal layout of each of the blocks forming the circuit that is the design target, merging all of the blocks and assembling the circuit as a chip, and analyzing the assembled circuit by performing a timing check or the like. When a timing adjustment or the like is preferred as a result of the analysis, the redesigning may again be required to perform the design operation from the start, namely, creating the internal layout of each of the blocks.
Therefore, according to the conventional circuit designing method using the hierarchical design technique, the degree of freedom of the routes between blocks forming the circuit that is the design target may be relatively small, and it may take a relatively long time for the design to converge.
The applicants are aware of Japanese Laid-Open Patent Publications No. 5-181929 and No. 6-52248.